1. Field of the Invention
The present invention relates to chip structures and fabrication methods thereof, and more particularly, to a chip structure having a redistribution layer and a fabrication method thereof.
2. Description of Related Art
Along with the development of electronic industries, electronic products have a trend towards multi-function and high performance. Currently, packaging substrates for carrying semiconductor chips can be such as wire bonding packaging substrates, chip scale packaging (CSP) substrates, flip chip ball grid array (FCBGA) packaging substrates and so on. To meet operational demands of microprocessors, chipsets and graphic chips, it is necessary to improve functions of the packaging substrates in chip signal transmission, improving bandwidth and controlling impedance so as to meet the development of packages with high I/O count.
Conventionally, a semiconductor chip with a plurality of electrode pads on a surface thereof is disposed to a packaging substrate with a plurality of conductive pads corresponding to the electrode pads, and a plurality of conductive bumps or other conductive adhesive material or gold wires are disposed between the semiconductor chip and the packaging substrate so as to electrically connect the semiconductor chip to the packaging substrate.
Further, a plurality of semiconductor packages can be stacked together to meet requirements for multi-function and high operating efficiency. In addition, redistribution layer (RDL) technology can be used to effectively utilize chip area so as to improve performance.
For example, U.S. Pat. No. 7,170,160 discloses a chip structure having a redistribution layer, wherein a plurality of chips is stacked together and electrically connected to each other through bonding wires.
FIG. 1A is an upper view of the chip structure as disclosed by U.S. Pat. No. 7,170,160, and FIG. 1B is a cross-sectional view of the chip structure. Referring to FIGS. 1A and 1B, a chip 10 with a plurality of electrode pads 11 disposed on a surface thereof is provided; a first passivation layer 12a is formed to cover the chip 10 and the electrode pads 11, and a plurality of first openings 120a is formed in the first passivation layer 12a for exposing the electrode pads 11, respectively; a redistribution layer 13 is formed on the first passivation layer 12a and conductive vias 130 are formed in the first openings 120a for electrically connecting to the electrode pads 11, respectively, wherein the redistribution layer 13 has a plurality of conductive pads 131 and widened portions 132, the widened portions 132 being used for improving the electrical performance of the structure; further, a second passivation layer 12b is formed to cover the first passivation layer 12a and the redistribution layer 13 and has a plurality of second openings 120b for exposing the conductive pads 131, respectively.
However, since the widened portions 132 having a large area are made of a metal material while the first passivation layer 12a or the second passivation layer 12b is made of a non-metal material, the bonding between the widened portion 132 and the second passivation layer 12b is quite poor, which easily results in delamination of the widened portions 132 from the second passivation layer 12b and thus reduces the quality of the electrical connection.
Therefore, it is imperative to provide a chip structure having a redistribution layer and a fabrication method thereof so as to overcome the above-described drawback.